TechQA.

Question

UVM agents - single/multiple?

score 53 · Answer 1 · 2024-03-13T07:59:40.940000

0

Answer

53

Views

UVM agents - single/multiple?

53 views Asked by G. B. At 13 March 2024 at 07:59

score 58 · Answer 2 · 2024-03-01T22:12:51.510000

UVM RAL: NULL pointer is dereference

58 views Asked by newbie99 At 01 March 2024 at 22:12

score 75 · Answer 3 · 2024-02-03T12:23:29.280000

Conditional creation of covergroup

75 views Asked by Rutuja14 At 03 February 2024 at 12:23

score 104 · Answer 4 · 2024-01-09T18:13:29.973000

Structure containing dynamic data in non-procedural context for parameterized test class

104 views Asked by thorondor1990 At 09 January 2024 at 18:13

score 104 · Answer 5 · 2023-12-21T18:53:44.993000

Can you use uvm_reg.get() on a volatile reg?

104 views Asked by Melandru's Square At 21 December 2023 at 18:53

score 187 · Answer 6 · 2023-12-06T08:27:56.827000

regexp in hdl path for UVM hdl access functions

187 views Asked by Alexandr Bolotnikov At 06 December 2023 at 08:27

score 297 · Answer 7 · 2023-11-19T06:52:03.863000

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

297 views Asked by Grace90 At 19 November 2023 at 06:52

score 82 · Answer 8 · 2023-11-10T17:40:59.700000

An abstract class cannot be instantiated in module

82 views Asked by Swathi Bardhabad At 10 November 2023 at 17:40

score 91 · Answer 9 · 2023-10-27T03:14:20.977000

Unexpected Queue Randomization with UVM environment

91 views Asked by 이정한 At 27 October 2023 at 03:14

score 163 · Answer 10 · 2023-09-15T19:45:36.357000

Is it possible to create a uvm-test dynamically from a string pased via UVM_TESTNAME but then override the base-test with the newly crearted test?

163 views Asked by Siraj Mubarak At 15 September 2023 at 19:45

score 532 · Answer 11 · 2023-09-07T07:36:44.073000

Is there any way to convert hierarchy as string to actual hierarchy

532 views Asked by robin tamrakar At 07 September 2023 at 07:36

score 127 · Answer 12 · 2023-08-29T09:19:46.217000

Constraint for square sub matrices in a matrix

127 views Asked by Grace90 At 29 August 2023 at 09:19

score 357 · Answer 13 · 2023-08-23T08:53:58.167000

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

357 views Asked by Grace90 At 23 August 2023 at 08:53

score 112 · Answer 14 · 2023-08-23T08:29:47.073000

Multi-master AXI interface connections

112 views Asked by Grace90 At 23 August 2023 at 08:29

score 191 · Answer 15 · 2023-08-22T23:29:10.393000

Why uvm_hdl_force has effect only in interactive mode in Verdi?

191 views Asked by Leo At 22 August 2023 at 23:29

score 218 · Answer 16 · 2023-08-14T04:05:04.637000

If a single test case can not make the functional coverage get nearly 100%, is it acceptable to use several test cases to hit every point?

218 views Asked by benjstark At 14 August 2023 at 04:05

score 252 · Answer 17 · 2023-08-05T20:26:06.670000

How to write UVM driver and sequence item for a vending machine design (interview question)?

252 views Asked by Grace90 At 05 August 2023 at 20:26

score 237 · Answer 18 · 2023-08-04T16:28:18.360000

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

237 views Asked by AnuragChauhan At 04 August 2023 at 16:28

score 268 · Answer 19 · 2023-08-01T11:46:37.527000

Can an agent have many drivers, many monitors and many sequencers?

268 views Asked by benjstark At 01 August 2023 at 11:46

score 119 · Answer 20 · 2023-07-26T09:14:20.023000

What should I do to make the interface visible to some components?

119 views Asked by benjstark At 26 July 2023 at 09:14

TechQA.

List Question

UVM agents - single/multiple?

UVM RAL: NULL pointer is dereference

Conditional creation of covergroup

Structure containing dynamic data in non-procedural context for parameterized test class

Can you use uvm_reg.get() on a volatile reg?

regexp in hdl path for UVM hdl access functions

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

An abstract class cannot be instantiated in module

Unexpected Queue Randomization with UVM environment

Is it possible to create a uvm-test dynamically from a string pased via UVM_TESTNAME but then override the base-test with the newly crearted test?

Is there any way to convert hierarchy as string to actual hierarchy

Constraint for square sub matrices in a matrix

I am trying to understand the way I can write a UVM scoreboard for a DUT (arbiter) with multiple masters and one slave

Multi-master AXI interface connections

Why uvm_hdl_force has effect only in interactive mode in Verdi?

If a single test case can not make the functional coverage get nearly 100%, is it acceptable to use several test cases to hit every point?

How to write UVM driver and sequence item for a vending machine design (interview question)?

Why uvm_driver class is not abstract class while other like class uvm_sequence also parameterized class but it is abstract one?

Can an agent have many drivers, many monitors and many sequencers?

What should I do to make the interface visible to some components?

Popular Questions

Trending Questions