readmemh reads values wrong

Question

module tb_alu32();
reg clk, reset;
reg [31:0] tb_a, tb_b, tb_yexpected;
reg [2:0] tb_op;
wire [31:0] tb_result;
reg[31:0] vectornum, errors;
reg[99:0] testvectors[10000:0];
...
always
begin
clk=0;#5;clk=1;#5;
end
$readmemh("C:/altera/13.0/practice/week3/alu32/testvect.tv",testvectors);
always @ (posedge clk)
begin
#1; {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];
end
endmodule

I read testvect.tv but tb_a and tb_b's MSB are missing and LSB is set 0 like

0000_0001->0000_0002
0000_0002->0000_0004
FFFF_FFFF->FFFF_FFFE
FFFF_FFFE->FFFF_FFFC 
8000_0001->0000_0002

How can I solve this? If I use readmemb, it works well.

If I assign values it works well.

Why did it happen?

Answer 1

This is what is causing the error Your {tb_a,tb_b,tb_op,tb_yexpected} = testvectors[vectornum];

LHS is 99 bits and RHS is 100 bits. Just declare

reg[98:0] testvectors[10000:0];

i.e instead of 100 bits, declare testvectors to be 99 bits.