I know this question has been answered some times already, but all those answers are specific to the according code. That's why I am asking it again. Why do I get this error and how do I fix it. I am trying to make a 8-bit up/down counter.
The error:
Error (10500): VHDL syntax error at UpDownCounter.vhd(30) near text "PROCESS"; expecting "if"
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all; -- needed for arithmetic increment
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY UpDownCounter IS
port( inA, inB : IN STD_LOGIC ;
Max_count: IN std_logic_vector(7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END UpDownCounter;
Architecture behavior of UpDownCounter is
signal internal_result : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
result <= internal_result;
PROCESS(inA, inB)
BEGIN
IF (inA'EVENT and inA = '1') THEN
IF internal_count < Max_count THEN
internal_result <= internal_result + 1;
END IF;
ELSIF (inB'EVENT and inB = '1') THEN
-- Check for maximum count
IF internal_count > Max_count THEN
internal_result <= internal_result - 1;
END IF;
ELSE
internal_result <= "00000000";
END PROCESS;
END behavior;
The help is appreciated!
In your code, the final ELSE is missing the terminating END IF.
This is for the previous ELSE IF and it's corresponding IF which must have an END IF; statement.