When I test my dataflow module, all my inputs come out as don't cares. I'm not sure where the problem lies. Could it be my equations or my testbench itself?
Here is my code.
Dataflow:
module TollSystem(weekDay,rushHour,lateNight,highTraffic,lowRate,mediumRate,highRate);
input weekDay,rushHour,lateNight,highTraffic;
output lowRate,mediumRate,highRate;
assign #6 lowRate = ~weekDay&~rushHour&lateNight&~highTraffic |
weekDay&~rushHour&lateNight&~highTraffic;
assign #6 mediumRate = (~rushHour&~lateNight&~highTraffic) | (~weekDay&~lateNight&~highTraffic) |
(rushHour&lateNight);
assign #6 highRate = (weekDay&~lateNight&rushHour) |
(~lateNight&highTraffic|~rushHour&lateNight&highTraffic);
endmodule
TestBench:
module TollSystemtest();
reg weekDay,rushHour,lateNight,highTraffic;
wire lowRate,mediumRate,highRate;
TollSystem TSys(weekDay,rushHour,lateNight,highTraffic,lowRate,mediumRate,highRate);
initial
begin
weekDay=0;rushHour=0;lateNight=0;highTraffic=0;
weekDay=0;rushHour=0;lateNight=0;highTraffic=1;
weekDay=0;rushHour=0;lateNight=1;highTraffic=0;
weekDay=0;rushHour=0;lateNight=1;highTraffic=1;
weekDay=0;rushHour=1;lateNight=0;highTraffic=0;
weekDay=0;rushHour=1;lateNight=0;highTraffic=1;
weekDay=0;rushHour=1;lateNight=1;highTraffic=0;
weekDay=0;rushHour=1;lateNight=1;highTraffic=1;
weekDay=1;rushHour=0;lateNight=0;highTraffic=0;
weekDay=1;rushHour=0;lateNight=0;highTraffic=1;
weekDay=1;rushHour=0;lateNight=1;highTraffic=0;
weekDay=1;rushHour=0;lateNight=1;highTraffic=1;
weekDay=1;rushHour=1;lateNight=0;highTraffic=0;
weekDay=1;rushHour=1;lateNight=0;highTraffic=1;
weekDay=1;rushHour=1;lateNight=1;highTraffic=0;
weekDay=1;rushHour=1;lateNight=1;highTraffic=1;
$finish();
end
endmodule
input/output results:
[1
When I run your code, the simulation ends at time 0. Since no time elapses, it is no surprise that your inputs are reported as x/z. You need to add delays in your testbench. For example:
Now, when I run a simulation and look at waveforms, I see all signals go to known values.
I added a delay of
#20
, but you should change that to something more meaningful to your design.