I am trying to do this in Verilog: when a button gets pressed (goes into state 1), I need a variable to be set to 1, and remain like that till I change it.
My code is:
always@(button)
begin
if(button==1) begin
var1=1;
end
end
But what I seem to get is that the var is set to 1 the whole program. How do I achieve my goal in a different way???
One of the reasons that you are getting always 1 might be, if the button is on the board, and you assigned that as an input, then they generally give output HIGH when not pressed and LOW when pressed. If that is the case use
if(button == 0)
as the condition.As you mentioned in commands you were using another always block to change the value of the variable, however you should not be able to change the same variable from two different always blocks. Hopefully we can find solutions that can solve your problem.
If your design is synchronous and clocked (generally it is the case in practical hardware designs), you can have something like this (it is practical if your clock has frequency that is larger than 10Hz):
Note: For this code to work, you have to press the pushbutton for longer time than clock period which is practically the case.
if the design is asynchronous, just include the button in your sensitivity list and write the code in the same always block.