MCHBAR Base Address Register (MCHBAR_0_0_0_PCI) — Offset 48h

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I'm trying to access the Secondary Plane Energy Status (SECP_NRG_STTS_0_0_0_MCHBAR_PCU register. The Intel documentation (https://www.intel.com/content/www/us/en/content-details/743846/13th-generation-intel-core-processors-datasheet-volume-2-of-2.html) denotes an offset of MCHBAR + 592Ch for this.

What is the MCHBAR address? - or how do i determine it?

Note: I'm running a Linux OS, and this is for a project related to energy consumption. Intel support has not been very helpful on this question. Low-level machine programming is not really my expertise, so I apologize, if my question is trivial or ignorant in any way.

I have read other documentation that suggests specific MSRs for reading RAPL energy status counters, but some of the values I get (specifically) PP1, does not seem correct at all. On asking Intel for help, they provided the above mentioned documentation(see link). I cannot make sense of it though.

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