In Yosys I am getting a Warning saying Literal has a width of 8 bit, can anyone elaborate on it since i am new to yosys and I could not find any resource to understand the reason for the warning.
below is the warnings from yosys:
Warning: Literal has a width of 8 bit, but value requires 16 bit. (../FPGA_memory/ROM_FPGA.v:1)
Warning: Literal has a width of 8 bit, but value requires 12 bit. (../FPGA_memory/ROM_FPGA.v:1)
Warning: Literal has a width of 8 bit, but value requires 12 bit. (../FPGA_memory/ROM_FPGA.v:1)
Warning: Literal has a width of 8 bit, but value requires 20 bit. (../FPGA_memory/ROM_FPGA.v:1)
Warning: Literal has a width of 8 bit, but value requires 16 bit. (../FPGA_memory/ROM_FPGA.v:1)
I figured it out, it was due to register "mem" initialisation using $readmemh("box.mif",mem,0,255); then I replaced it with $readmemh("box.mem",mem);. This line resolved the warning.
"box.mem" file was created as explained in https://projectf.io/posts/initialize-memory-in-verilog/#:~:text=Verilog%20Syntax,%24readmemb(%22bin_memory_file.
I created this .mif file from altera quartus IDE but was not aware It can not be used in $readmemh.