In risc-v architecture, how does store conditional instruction realize that the memory is modified?

Question

The following code snippet is from Computer Organization and Design, RISC-V edition, 2nd edition.

Suppose that the memory location that is addressed by x20 register is modified after execution of lr.w instruction and before execution of sc.w. My Question is that how does the sc.w instruction realize that the content of the memory location is changed.

again:
lr.w x10, (x20)       // load-reserved
sc.w x11, x23, (x20)  // store-conditional
bne x11, x0, again    // branch if store fails (0)
addi x23, x10, 0      // put loaded value in x23