In ARMv7, is the address used in TTBR0 and TTBR1 physical or virtual

Question

I've been looking in the ARM Architecture Reference Manual for v7-A and v7-R in Section B3 and I can't figure out if the address used in the TTBR0 and TTBR1 registers is supposed to be a virtual or physical address.

Physical would make the most sense, but I'd like to know definitively.

So, is this address supposed to be physical or virtual?

Is it required to keep the page table location mapped as an identity address (PA == VA)?

Answer 1

Imagine it were a virtual address...

The CPU issues a transaction to a virtual address. In order to translate it, the MMU needs to do a table walk. For that it needs to know what bit of RAM to address on the bus, so it looks in the base register. Great, now it has the virtual base address, it just needs to translate that to a physical address to know what bit of RAM to address on the bus, so it needs to do a table walk. For that it needs... etc. etc.

In short, yes, they're definitely physical addresses. The fact that TTBRn are 64-bit on LPAE implementations is also a bit of a clue.^*

Once the page tables are set up and the MMU is on, it's not required to keep them mapped at all, let alone in any particular relationship - if the data's physically there in RAM, the MMU is quite happy. The CPU only needs to map that RAM into its address space if it's updating the tables - the rest of the time they'd just be a waste of address space.

_{* ...and this is of course a complete lie when the Virtualisation Extensions are involved ;) In that case, they're intermediate physical addresses, and entirely subject to the whims of stage 2 translation. For which the above applies. Fun.}

Answer 2

Physical. In this regard it is unchanged from the ARMv5.

Answer 3

As per the code, Physical address of pgd is written to TTBR.

http://lxr.free-electrons.com/source/arch/arm/include/asm/proc-fns.h#L116

#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)