Im trying to make a right/left shifter using verilog but my output is xxxxx

Question

module MyProject(A,B,k,right,F);
  input [31:0]A;
  input [31:0]B;
  input [4:0]k;
  input right;
  output reg [31:0]F;
  reg [31:0]F1;
  integer i,j;
  initial
  begin
  assign F1=(A&~B)+(~A&B);
  for(j=0;j<k;j=j+1)
    begin
      if(right==1)
        begin
          for(i=0;i<32;i=i+1)
          begin
            F1[i]=F1[i+1];
            if(i==31)
            F1[i]=0;
          end
        end
      else if(right==0)
        begin
          for(i=31;i>-1;i=i-1)
          begin
            F1[i]=F1[i-1];
            if(i==0)
              F1[i]=0;
          end
        end
    end
    for(i=0;i<32;i=i+1)
      F[i]=F1[i];
    //F=F1;
  end

endmodule

Answer 1

Your code got a little jumbled in the question - here's the original question with the Enter Code Here lines replaced with new lines:

module MyProject(A,B,k,right,F);
input [31:0]A;    
input [31:0]B;    
input [4:0]k;    
input right;    
output reg [31:0]F;    
reg [31:0]F1;    
integer i,j;    
initial    
   begin    
   assign F1=(A&~B)+(~A&B);    
   for(j=0;j    
   begin    
   if(right==1)    
     begin    
        for(i=0;i<32;i=i+1)    
           begin    
              F1[i]=F1[i+1];      
              if(i==31)    
              F1[i]=0;    
          end    
    end    
     else if(right==0)    
        begin    
         for(i=31;i>-1;i=i-1)    
           begin    
              F1[i]=F1[i-1];    
             if(i==0)    
                F1[i]=0;    
           end    
      end    
   end    
  for(i=0;i<32;i=i+1)    
     F[i]=F1[i];    
  //F=F1;    
 end    
endmodule    

I am guessing the objective is to perform a logical operation on the inputs A and B, and then generate a shifted output. I think you are close, but there a few things that should be corrected:

1. The function just has an initial block, so it gets run once when the simulator starts up, and it never runs again. You didn't mention if the assignment was to create a function that continuously generates output F (i.e. a bunch of gates with no registers) or a function that evaluates "A/B/k/right" on a clock edge, and then generates the output. If you are creating a combinatorial function, when you would need to replace the "initial" with something like "always @*" which will re-run the function every time an input value changes, and you will also need to change the reg's to wires. If you are creating a registered block, you will need to add a clock. You might look at this code for a good example of a clocked shift register.

2. There is an assign statement inside the initial block. Assign statements represent expressions that are always true in Verilog, so they go outside of procedural blocks. The assign statement assigns a value to a register - assign statements should be paired with wires.

3. The procedural code uses the F1 register as the input and output, but F1 has already been assigned a value. I would suggest breaking this up into two steps, mainly compute (A&~B)+(~A&B) and assign that to F1. Then write a procedural block to perform the shifting of F1 into the output, which could be a wire or register depending on the answer to #1

Hope that helps.