How to use multiple Verilog files in Quartus

Question

I am learning Verilog with Altera's (now Intel) Quartus Prime development s/w and a DE0_Nano Cyclone IV dev board. I have the Charles Roth et al book "Digital Systems Design Using Verilog" which seems very good at the Verilog module level. I have also looked through a number of on line tutorials and I have a project working using a single Verilog file which is fine as far as it goes.

What I am missing and cannot find any guidance on is how to split a project into multiple hierarchical Verilog source files. I only want the hierarchy's top level file with the top level module instantiated in the Quartus project's .bdf file (the top level of the project drawn like a circuit).

Anyone any ideas how to do this? I presume simply including the lower level files in the top level Verilog file (via `include directive) is not the best way to do it. (Although do doubt it would work)

Help appreciated, John

Answer 1

First, create your subcircuit (either in HDL or as a schematic/BDF file). Once your done, save it, and with the subcircuit file open, select File->Create/Update->Create Symbol Files for Current File.

Then, go to your top-level schematic, and click on the Symbol tool. In addition to the standard list of primitives, you should see a group of "Project" symbols. In there, you should find a block for your subcircuit to include in the top-level module.

Answer 2

Just add the Verilog files to the project: Project -> Add/Remove Files in Project... They will be compiled and instantiated as necessary.