How to trace an uninitialized signal in Chisel?

Question

We have a complex design and occasionally forget to initialize a signal. Chisel assigns a random value. But this makes it difficult to trace backwards from the point at which the error is detected, back to the origin. There are warnings about uninitialized signals, but this is not helpful for the reason that there are many signals that we intentionally leave uninitialized because they don't propagate. Only in a tiny few cases, such as for "valid" signals, does an uninitialized signal propagate and cause problems. The ideal would be what verilog does, which is set the value to "x", which allows easily tracing it backwards. Is there any relatively painless way of finding these cases with uninitialized signals that cause problems?

Answer 1

In Chisel 3, we are currently in the process of adding safety for unconnected signals: https://github.com/ucb-bar/chisel3/issues/413. I'm not sure what the outcome will be, but our goal is to prevent exactly the kind of issues mentioned here.