I have to use the Cadence program suite to complete a Verilog class assignment and I'd like to know why $display
statements in the very simple mock-testbench I have created do not produce output in the SimVision console window.
My workflow goes like this: I have created a cell with the following functional view:
module tesbench ( );
initial begin
$display("RUNNING TESTBENCH");
$finish;
end
endmodule
I have then invoked NC-Verilog, initialized and netlisted and simulated the cell which opens the SimVision console window. Running the simulation then produces the following output:
ncsim> run
Simulation complete via $finish(1) at time 0 FS + 0
/home/path/to/verilog/file.v:4 $finish;
ncsim>
So $display
output is not shown. This seems like a very simple problem but I cannot for the life of me figure out what I'm doing wrong.
Okay, so I have just been able to speak with an instructor and he told me that this is a known problem with the installation and that there is currently no work-around (the programs are running on a server administrated by the university).