How to initialize ShiftRegister primitive in Chisel

Question

We are using ShiftRegister in Chisel 2 to implement a delay. But it's not clear how to force it to initialize to a value of our choosing, such as forcing it to zero (NOT random). How to do this?

Answer 1

I have not much with Chisel 2, but I believe this ShiftRegister.apply method should work.

In Chisel 3, there is an open PR to add this functionality. Without this PR, it is still possible as follows:

val shiftIn = Wire(UInt(32.W))
val shiftReg = ShiftRegister(Mux(reset, RESET_VALUE, shiftIn), n)

Just connect to shiftIn to input to the shiftReg.