I have build a JK FlipFlop in Logisim to further use it as subcircuit.
The Problem is that when you place that subcircuit it will start with the red colored exit pins. The FlipFlop is also depending on the information of the state of the outputs, 1 or 0.
The Question is if there is a way to avoid this undefined state somehow.
I Know that i could just use the SR-FlipFlop included in Logisim because this will be placed without errors on the Outputs from the start but I would like to build every part myself if it is possible.
I do not know of an explicit way to prevent the red lines. However, you can "initialize" it by enabling K on the rising edge of the clock - this will clear the red lines and begin normal operations.
Hope this helps, I'll return if I find a better answer.