How can i implement byte addressable memory in VHDL?

Question

I want to make 4kb byte addressable memory. sorry I'm new in VHDL

I wanted my code works first write 4byte number in adress 8 (rdwr=1, addr=1000, size=10(2^2byte), idata=10001100)

then wait 8 cycles to implement writing time(ivalid=0)

Second read 4byte number from adress 8(rdwr=0, addr=1000, size=10(2^2byte))

In my purpose, the "ready" signal should be '0' while waiting for writing time but the signal is always 'U' in simulation. I tried to figure out what is the problem but i couldn't

Can anyone help me where did a make mistake?

Here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Memory is
port (
    clk: in std_logic;

    ready: out std_logic;   -- 0: busy, 1: ready

    ivalid: in std_logic;   -- 0: invalid, 1: valid
    rdwr: in std_logic;                     -- 0: read, 1: write
    addr: in unsigned(11 downto 0);         -- byte address
    size: in std_logic_vector(1 downto 0);  -- 00/01/10/11: 1/2/4/8 bytes
    idata: in std_logic_vector(63 downto 0);

    ovalid: out std_logic;  -- 0: invalid, 1: valid
    odata: out std_logic_vector(63 downto 0)
);
end entity;

architecture Behavioral of Memory is
type ram_type is array (0 to (2**12)-1) of std_logic_vector(7 downto 0);
signal RAM : ram_type;
signal state : std_logic := '1'; --if ready '1'
signal queue : std_logic := '0'; --if something to do '1'
signal timer : integer := 0; --timer
signal curr_addr : unsigned(11 downto 0); 
signal curr_size : std_logic_vector(1 downto 0);
signal curr_data : std_logic_vector(63 downto 0);
signal write : std_logic := '0';
signal read : std_logic := '0';
begin
process(clk)
variable vstate : std_logic := state;
variable vqueue : std_logic := queue; --if something to do '1'
variable vtimer : integer := timer; --timer
variable vcurr_addr : unsigned(11 downto 0) := curr_addr; 
variable vcurr_size : std_logic_vector(1 downto 0) := curr_size;
variable vcurr_data : std_logic_vector(63 downto 0) := curr_data;
variable vwrite : std_logic := write;
variable vread : std_logic := read;

begin
    --get input
    if(rising_edge(clk)) then  
        ovalid <= '0';
        if(vstate='1') then
            if(ivalid='1') then
                vcurr_addr := addr;
                vcurr_size := size;
                if(rdwr='0') then
                    --read
                    vread := '1';
                else
                    vwrite := '1';
                    vcurr_data := idata; 
                end if;
                vqueue := '1';
                vtimer := 2**(to_integer(unsigned(vcurr_size)))-1;
            end if;
        end if;

        --process
        if(vqueue = '1') then
            if(vtimer > 0) then
            --wait for next cycle
                ready <= '0';
                vstate := '0';               
                vtimer := vtimer - 1;
            else
            --ok to go
                if(vwrite = '1') then
                --write
                    for x in 0 to 2**(to_integer(unsigned(vcurr_size)))-1 loop
                        for y in 0 to 7 loop
                            RAM(to_integer(vcurr_addr) + x)(y) <= vcurr_data(y + 8*x);                              
                        end loop;
                    end loop;                       
                elsif(vread = '1') then
                --read
                    for x in 0 to 7 loop
                        for y in 0 to 7 loop
                            if(x < 2**(to_integer(unsigned(vcurr_size)))) then
                                odata(y + 8*x) <= RAM(to_integer(vcurr_addr) + x)(y);
                            else 
                                odata(y + 8*x) <= '0';
                            end if;
                        end loop;
                    end loop; 
                    ovalid <= '1';                           
                end if;  
                vqueue := '0';
                vstate := '1';
                ready <= '1';                               
            end if;     
        end if;

        --save variable to signals
        state <= vstate;
        queue <= vqueue;
        timer <= vtimer;
        curr_addr <=vcurr_addr;
        curr_size <=vcurr_size;
        curr_data<= vcurr_data;
        write <= vwrite;
        read <= vread;
  end if;      
end process;
end architecture;