I'm using the following tools for programing in verilog+system-verilog and I'm wondering which can detect which variables are not being in use:
- Eclipse
- Eclipse DVT extension
- Cadence tools
Find unused variables
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Related Questions in VERILOG
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Related Questions in SYSTEM-VERILOG
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- Is it possible to find an element in a Vec<T> and remove it?
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- Creating byte buffers in rust
Related Questions in CADENCE
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- unresolved name rand::thread_rng
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I don't think DVT can detect unused variables, but AMIQ have another product called Verisimo that can do this, AFAIK.
Also, try using the HAL (HDL Advanced Linter) from Cadence to see if they support this (it's a pretty basic thing for a linter).