Enabling one timer using another

Question

I want to make STM32F042K6 to output two same PWM signals shifted 180 degrees one to another. For that purpose, I use two STM32 timers in master-slave configuration (TIM2 and TIM3 respectively). TIM2 outputs two signals: one to the external pin PA0, while another one is the trigger for TIM3 (TIM3 is configured in Slave Mode - Trigger mode). What I mentioned is that TIM3 works even when TIM2(master) is not enabled by writing TIM2->CR1 |= TIM_CR1_CEN; Therefore, I assume there is no interdependence between TIM2 and TIM3 in my code. Here is my code:

void TIM2_setup(void){
// Enable Timer 2 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
// I/O port A clock enable
RCC->AHBENR |= RCC_AHBENR_GPIOAEN;

//These bits are written by software to configure the I/O mode. Port x configuration I/O pin y ( Port A, 10: Alternate function mode)
GPIOA->MODER |= (0x2UL << GPIO_MODER_MODER0_Pos);
//GPIOA->MODER |= (0x2UL << GPIO_MODER_MODER1_Pos);

//Alternate function AF1 selection. Alternate function selection for port x pin y (y = 0..7)
GPIOA->AFR[0] |= (0x2UL << GPIO_AFRL_AFSEL0_Pos);   // PA0
//GPIOA->AFR[0] |= (0x2UL << GPIO_AFRL_AFSEL1_Pos); // PA1

// Center-aligned mode 3 selection. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down
TIM2->CR1 |= TIM_CR1_CMS;
// : PWM mode 1
TIM2->CCMR1 |= (0x6UL << TIM_CCMR1_OC1M_Pos);
TIM2->CCMR1 |= (0x6UL << TIM_CCMR1_OC2M_Pos);
// Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
TIM2->CCMR1 |= TIM_CCMR1_OC1PE;
TIM2->CCMR1 |= TIM_CCMR1_OC2PE;
//OCx signal is output on the corresponding output pin
TIM2->CCER |= TIM_CCER_CC1E;
TIM2->CCER |= TIM_CCER_CC2E;

// MASTER MODE CONFIGURATION
// OC2REF signal is used as trigger output 
TIM2->CR2 |= (0x5UL << TIM_CR2_MMS_Pos);
// Output Compare 2 mode. Set channel 2 to active level on match.
TIM2->CCMR1 |= (0x1UL << TIM_CCMR1_OC2M_Pos);

TIM2->ARR = 8;
TIM2->CCR1 = 6;
TIM2->CCR2 = 0;
TIM2->PSC = 0;
TIM2->CNT = 0;
TIM2->CR1 |= TIM_CR1_ARPE;}

void TIM3_setup(){
// Enable Timer 3 clock
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
// I/O port A clock enable (setovano u TIM2_setup())
RCC->AHBENR |= RCC_AHBENR_GPIOAEN;

// These bits are written by software to configure the I/O mode. Port x configuration I/O pin y ( Port A, 10: Alternate function mode)
GPIOA->MODER |= (0x2UL << GPIO_MODER_MODER6_Pos);
// Alternate function selection for port x pin y (y = 0..7) (port A, pin 6)
GPIOA->AFR[0] |= (0x1UL << GPIO_AFRL_AFSEL6_Pos);   //PA6


// Center-aligned mode 3 selection. The counter counts up and down alternatively.
TIM3->CR1 |= TIM_CR1_CMS;
//PWM mode 1
TIM3->CCMR1 |= (0x6UL << TIM_CCMR1_OC1M_Pos);
// Preload register on TIMx_CCR1 enabled.
TIM3->CCMR1 |= TIM_CCMR1_OC1PE;
//OCx signal is output on the corresponding output pin
TIM3->CCER |= TIM_CCER_CC1E;

// SLAVE MODE CONFIGURATION
// Slave mode selection 110: Trigger Mode
TIM3->SMCR |= (0x6UL << TIM_SMCR_SMS_Pos);
// Trigger selection TS=001 --> TIM2
TIM3->SMCR |= (0x1UL << TIM_SMCR_TS_Pos);
//Capture/Compare 1 selection. CC2 channel is configured as input, IC2 is mapped on TI2
TIM3->CCMR1 |= (0x1UL << TIM_CCMR1_CC2S_Pos);

TIM3->ARR = 8;
TIM3->CCR1 = 6;
TIM3->PSC = 0;
TIM3->CNT = 0;
TIM3->CR1 |= TIM_CR1_ARPE;}

void TIM2_enable(){
TIM2->CR1 |= TIM_CR1_CEN;}

void TIM3_enable(){
TIM3->CR1 |= TIM_CR1_CEN;}

Probably I messed up with some registers, but in this moment I am very confused.