Do RISC processors not have backward compatibility?

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I'm reading a textbook which says:

RISC processors have done very well in the market for embedded processors, controlling such systems as cellular telephones, automobile brakes, and Internet appliances. In these applications, saving on cost and power is more important than maintaining backward compatibility.

Does it mean RISC processors (e.g. ARM) are not backward compatible with older versions?

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Peter Cordes On BEST ANSWER

That's correct; for example on really old ARM, a word load with non-zero low bits meant to rotate an aligned word. On modern ARM, those bits are just part of the address and give you an unaligned load.

So ARM at one point subtly broke compat with rare code which depended on that feature, making those old binaries unusable on modern ARM. Most ARM binaries are still fine because they avoided unaligned word loads/stores entirely.

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phuclv On

Another example is MIPS

Typically when a new ISA version is introduced then instructions are added but old instructions are still left as-is for backward compatibility. For example in x86 many instructions that no one uses for decades are still valid and supported until now. However in MIPS III a few instructions were removed to free up some opcodes. Then after MIPS V when MIPS Technologies split off from SGI, a major overhaul was introduced: MIPS32/MIPS64. The naming scheme was changed and some more instructions were removed

  • some conditional moves
  • branch likely instructions (deprecated in previous releases).
  • integer overflow trapping instructions with 16-bit immediate
  • integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)
  • unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))

MIPS32/MIPS64

It also "Reorganized the instruction encoding, freeing space for future expansions."

One of the reasons for that is probably because MIPS changed their focus from high performance systems to embedded systems