Cortex-M external interrupt occurs when executing fault handler with higher priority

Question

What happens when a lower priority interrupt from a peripheral occurs while the cortex-m is executing a higher priority fault handler? Will it be ignored or will it trigger a hardfault?

Answer 1

If a higher priority interrupt is being serviced, the lower-priority interrupt will remain pending. Once the higher priority ISR completes, the lower-priority interrupt will be serviced. Multiple interrupts can be in the pending state waiting to be handled. They will be handled in order of their priority.

In addition, Cortex-M CPUs have a feature called tail-chaining. This means that when the higher-priority ISR completes, it does not need to pop all the saved registers from the stack, only for them to get pushed again when the low-priority ISR gets run. Instead, the lower-priority ISR gets called directly, then when it exits, it will pop the saved registers.