connecting VHDL port to system verilog interface definition in UVM

Question

I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition:

TYPE loop_reg_ty IS RECORD
      loop_index_value    : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_end_flag : std_logic;
END RECORD;

TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of loop_reg_ty;

One of the VHDL output ports in my DUT is of type loop_array_ty;

I am trying to define the SystemVerilog equivalent as:

typedef struct packed {
                            bit [REG_BITWIDTH-1:0] loop_index_value;
                            bit [REG_BITWIDTH-1:0] loop_counter;
                            bit loop_end_flag;
                          } raccu_loop_reg_ty;

typedef raccu_loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;

When I use irun, I get the error:

VHDL port type is not compatible with Verilog.

Please suggest the possible work around solution.

Answer 1

First, your problem is that you're not defining the loop_array_ty correctly. It should be typedef raccu_loop_reg_ty loop_array_ty[MAX_NO_OF_RACCU_LOOPS-1:0].

I would suggest 2 things here:

First, try removing the packed qualifier from the struct definition. Connecting SV structs to VHDL records is something that is only available in newer Incisive versions. Make sure that the version you're using supports this.

If you're using an older version of Incisive (like I was a year back), your only choice is to map the individual record members using $nc_mirror (not tested code, but enough to get you started):

// struct definition...
// ...

module top;
  // intermediate signal we'll mirror onto
  loop_array_ty loop_s;

  // no output connected
  my_dut dut_inst();

  // make the connection between SV and VHDL using nc_mirror
  initial begin
    for (int i = 0; i < MAX_NO_OF_RACCU_LOOPS; i++) begin
      $nc_mirror($sformatf("loop_s[%0d].loop_index_value", i),
        $sformatf("dut_inst.loop_o[%0d].loop_index_value", i);

      // $nc_mirror for loop_counter
      // $nc_mirror for loop_end_flag
    end
  end
endmodule

Also make sure that you're setting the REG_BITWIDTH constant appropriately in both languages, otherwise you'll also get a type mismatch.