Array initialization error in Verilog

Question

I made a code like this:

input [7:0] Address, WriteData;
input MemRead = 0, MemWrite = 0, CLK;
output reg[7:0] ReadData;

reg [31:0] Input[7:0], Output[7:0];
reg [31:0] Sel;
wire [4:0] addr = Address[4:0];
integer i;

initial begin
    for(i = 0; i < 16; i = i + 1) begin
        Output[i] = i;
        Output[15 + i] = 255 - i + 1;
    end
    Sel = 32'b0;        
end


always @(MemRead or MemWrite) begin
    if(MemRead == 1) begin
        ReadData <= Output[7]; // here is error point
    end
    else if(MemWrite == 1) begin
        Input[addr] <= WriteData;
        Sel[addr] <= MemWrite;
    end
end 

It initializes array Output like:

Output[0] = 0, Output[1] = 1, Output[2] = 2...

When I gave ReadData <= Output[number] with number < 8, and simulate, it gives expected result: ReadData = 00000111 for Output[7].

But, when I gave number >= 8, result changes: ReadData = XXXXXXXX for Output[8].

I did not changed anything but the number. How can this happen?

Answer 1

You declared Output as following:

reg [31:0] Output[7:0];

It means that you have 8 vectors, 32 bits each. Judging by your confusion and one of your loops, I'd say that you want 32 vectors, 8 bits (1 byte) each. In that case, you should declare Output as:

reg [7:0] Output [31:0];

Btw you should rather avoid naming your signals almost like Verilog keywords (input, output, etc)