I am trying to rewrite a code section that currently works with disabling/enabling interrupts with LDREX/STREX on a STM32F7(single core, microcontroller).
May sound like a straightforward question, but after a couple of days researching, did not seem to find a definitive answer neither in ARM documentation, nor in community replies:
Would a regular memory access between LDREX/STREX invalidate the exclusive monitor state (and hence always fail STREX)?
Common sense is that it should be invalidated, but still ARM documentation does not state regular memory accesses as one of the cases which invalidate the exclusive monitor.
It is a fact that in most situations the work between LDREX and STREX can be done only in registers, so the question will not be relevant, but in my case this does not suffice and I need to access memory. I am basically trying to do a detector "did an interrupt occur between these lines?"
The ST manual states that the EGR is the whole memory, but still it does not answer the question.
Code section:
failed:
LDR R2, =g_Exclusive_Var
LDREX R0, [R2]
...
LDR ... ---> is this OK
STR ... ---> is this OK
...
STREX R3, R0, [R2]
CMP R3, #0
BNE failed