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SSE for 2D arrays

score 290 · Answer 1 · 2021-03-08T19:32:45.567000

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SSE for 2D arrays

290 views Asked by Antreas Petrou At 08 March 2021 at 19:32

score 1018 · Answer 2 · 2020-10-29T13:42:31.060000

convertion of four packed single precision floating point to unsigned double words in x86-SSE

1k views Asked by Iman Abdollahzadeh At 29 October 2020 at 13:42

score 284 · Answer 3 · 2020-06-27T03:42:55.317000

Adding horizontally with SSE3

284 views Asked by julix At 27 June 2020 at 03:42

score 1227 · Answer 4 · 2019-05-21T12:21:45.547000

What is the difference between _mm_movehdup_ps and _mm_shuffle_ps in this case?

1.2k views Asked by ThreeStarProgrammer57 At 21 May 2019 at 12:21

score 2634 · Answer 5 · 2016-10-20T09:17:30.453000

Processor optimization flags in OpenCV

2.6k views Asked by 4-bit At 20 October 2016 at 09:17

score 3305 · Answer 6 · 2016-05-02T15:01:12.357000

How to use vectors in assembly code x86 and SSE

3.3k views Asked by Manuel Minguez At 02 May 2016 at 15:01

score 3002 · Answer 7 · 2015-06-26T15:01:11.317000

(Vec4 x Mat4x4) product using SIMD and improvements

3k views Asked by Asohan At 26 June 2015 at 15:01

score 246 · Answer 8 · 2015-05-08T05:41:41.103000

MinGW error Type '__m128i' could not be resolved in eclipse

246 views Asked by Mohan At 08 May 2015 at 05:41

score 534 · Answer 9 · 2015-05-02T21:40:35.987000

Converting 24 to 16 bit audio using SSE/simd instructions

534 views Asked by ohrfritz At 02 May 2015 at 21:40

score 3527 · Answer 10 · 2015-01-30T00:09:01.850000

converting from int to (16-bit) __m128i

3.5k views Asked by MROF At 30 January 2015 at 00:09

score 437 · Answer 11 · 2014-02-22T09:15:07.310000

Intel intrinsics support for Atom cloverview processor

437 views Asked by Harrisson At 22 February 2014 at 09:15

score 839 · Answer 12 · 2014-02-21T07:30:33.590000

Performance degrade while using alternative for Intel intrinsics SSSE3

839 views Asked by Harrisson At 21 February 2014 at 07:30

score 134 · Answer 13 · 2013-11-20T20:16:13.507000

Reading file with "gaps" in destination array

134 views Asked by Arokh At 20 November 2013 at 20:16

score 1467 · Answer 14 · 2013-11-03T11:39:24.127000

SIMD integer store

1.4k views Asked by Thudor At 03 November 2013 at 11:39

score 4013 · Answer 15 · 2013-07-16T07:52:14.960000

How to enable SSSE3 intrinsics but disable their use in compiler optimization

4k views Asked by Mark S At 16 July 2013 at 07:52

score 1081 · Answer 16 · 2013-07-01T14:53:00.980000

AVX and Bubble Sort

1k views Asked by Frank At 01 July 2013 at 14:53

score 8981 · Answer 17 · 2013-02-15T11:36:41.180000

C++ SSE3 instruction set not enabled

8.9k views Asked by Aditya Sihag At 15 February 2013 at 11:36

score 309 · Answer 18 · 2012-09-29T20:24:06.327000

ROS (Robot Operating System) with SSSE3 flag

309 views Asked by SolvedForHome At 29 September 2012 at 20:24

score 1040 · Answer 19 · 2012-09-12T18:14:59.243000

Memory Access Violations When Using SSE Operations

1k views Asked by Eric Foote At 12 September 2012 at 18:14

score 841 · Answer 20 · 2012-07-19T11:08:05.363000

Should I compile with -mssse3 in the presence of ASM SSSE3 code?

841 views Asked by Philos At 19 July 2012 at 11:08

TechQA.

List Question

SSE for 2D arrays

convertion of four packed single precision floating point to unsigned double words in x86-SSE

Adding horizontally with SSE3

What is the difference between _mm_movehdup_ps and _mm_shuffle_ps in this case?

Processor optimization flags in OpenCV

How to use vectors in assembly code x86 and SSE

(Vec4 x Mat4x4) product using SIMD and improvements

MinGW error Type '__m128i' could not be resolved in eclipse

Converting 24 to 16 bit audio using SSE/simd instructions

converting from int to (16-bit) __m128i

Intel intrinsics support for Atom cloverview processor

Performance degrade while using alternative for Intel intrinsics SSSE3

Reading file with "gaps" in destination array

SIMD integer store

How to enable SSSE3 intrinsics but disable their use in compiler optimization

AVX and Bubble Sort

C++ SSE3 instruction set not enabled

ROS (Robot Operating System) with SSSE3 flag

Memory Access Violations When Using SSE Operations

Should I compile with -mssse3 in the presence of ASM SSSE3 code?

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