I have generated the ELF file and I am able to generate the Verilog format using riscv64-unknown-elf-objcopy tool. The problem is I have compressed instructions like below, but I am parsing the file in my Verilog testbench, so I need to know where the boundary of every instruction is. Any idea how to solve this issue? Would it be possible to pad the register length by using any arguments of riscv tool? An idea could be de-assemble the ELF file, zero pad the register related to compressed instructions and save the new ELF (how?) from where I will be generating the new Verilog file.
40000: 00000297 auipc t0,0x0
40004: 05628293 addi t0,t0,86 # 40056 <__text.init_start+0x56>
40008: 30529073 csrw mtvec,t0
4000c: 4081 li ra,0
4000e: 4181 li gp,0
Verilog version:
`@00040000
97 02 00 00 93 82 62 05 73 90 52 30 81 40 81 41
01 42 81 42 01 43 81 43 01 44 81 44 01 45 81 45
01 46 81 46 01 47 81 47 01 48 81 48 01 49 81 49`
Thank you, S.