Zephyr/NXPproject: add own board to the board path(based on the IMXRT1170_evk)

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I'm trying to add a new board to the board folder of the zephyr project.

Goal: I want to boot from the flash via the FLEXSPI1 of my microcontroller (IMXRT1176...A - CM7) and using tcm instead of SDRAM or any external RAM. I'm not using the evk from NXP, but another board.

Toolchain and build: Build Toolchain

Using jlink v. 7.66 with an own device proper for the pin muxing change.

So far I tried this:

1. Changing the pinctrl.dtsi

I changed the pinctrl.dtsi, because the flexspi in use has another pin muxing. I couldn't find something about changing the pinmuxing of the devicetree... This change was based on hope.

#include <nxp/nxp_imx/rt/mimxrt1176dvmaa-pinctrl.dtsi>
...
    };
    
    pinmux_flexspi1: pinmux_flexspi1 {
        group0 {
            pinmux = <&iomuxc_gpio_sd_b2_05_flexspi1_a_dqs>,
                <&iomuxc_gpio_ad_18_flexspi1_a_ss0_b>,
                <&iomuxc_gpio_ad_19_flexspi1_a_sclk>,
                <&iomuxc_gpio_ad_20_flexspi1_a_data00>,
                <&iomuxc_gpio_ad_21_flexspi1_a_data01>,
                <&iomuxc_gpio_ad_22_flexspi1_a_data02>,
                <&iomuxc_gpio_ad_23_flexspi1_a_data03>;
            bias-pull-down;
            input-enable;
        };
    };
...

2. Changed the devicetree

/*
 * Copyright 2021-22, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <nxp/nxp_rt11xx_cm7.dtsi>

/ {
    model = "NXP TQMBA117x board";
    compatible = "nxp,mimxrt1176";

    aliases {
        watchdog0 = &wdog1;
    };

    chosen {
        zephyr,sram = &dtcm;
        //zephyr,dtcm = &dtcm;
        zephyr,itcm = &itcm;
        zephyr,console = &lpuart1;
        zephyr,shell-uart = &lpuart1;
        zephyr,flash = &mt25qu256;
        zephyr,cpu1-region = &ocram;
        zephyr,ipc = &mailbox_a;
    };

    sdram0: memory@80000000 {
        /* Winbond W9825G6KH-5I */
        device_type = "memory";
        reg = <0x80000000 DT_SIZE_M(256)>;
    };
};

&flexspi {
/delete-node/ is25wp128@0;
status = "okay";
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>;
mt25qu256:mt25qu256@0 {
    compatible = "nxp,imx-flexspi-nor";  // Use your driver's compatible string
    size = <DT_SIZE_M(256)>;  // Size of MT25QU256ABA8E12-1SIT
    reg = <0>;
    spi-max-frequency = <166000000>;  // Max SPI frequency in STR mode
    status = "okay";
    jedec-id = [ba 19 00];  // JEDEC ID
    erase-block-size = <65536>;  // 64KB sector erase granularity
    write-block-size = <1>;  // Minimum write block size

    /*
        * Partitions are present to support dual core operation.
        * as flash write is not supported, MCUBoot is not enabled.
        */
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        boot_partition: partition@0 {
            label = "mcuboot";
            reg = <0x00000000 DT_SIZE_K(128)>;
        };
        /* Note slot 0 has one additional sector,
            * this is intended for use with the swap move algorithm
            */
        slot0_partition: partition@20000 {
            label = "image-0";
            reg = <0x00020000 0x301000>;
        };
        slot1_partition: partition@321000 {
            label = "image-1";
            reg = <0x00321000 0x300000>;
        };
        scratch_partition: partition@621000 {
            label = "image-scratch";
            reg = <0x00621000 DT_SIZE_K(128)>;
        };
        storage_partition: partition@641000 {
            label = "storage";
            reg = <0x00641000 DT_SIZE_K(1856)>;
        };
        };
    };
};

zephyr_lcdif: &lcdif {};

zephyr_mipi_dsi: &mipi_dsi {
    dphy-ref-frequency = <24000000>;
};

&lpuart1 {
    status = "okay";
    current-speed = <115200>;
};

&flexcan3 {
    status = "okay";
    bus-speed = <125000>;
    bus-speed-data = <1000000>;
    can-transceiver {
        max-bitrate = <5000000>;
    };
};

&lpspi1 {
    status = "okay";
};

nxp_mipi_i2c: &lpi2c5 {
    pinctrl-0 = <&pinmux_lpi2c5>;
    pinctrl-names = "default";
    #address-cells = <1>;
    #size-cells = <0>;
};

&lpadc0 {
    status = "okay";
};

&usdhc1 {
    status = "okay";
    detect-dat3;
    pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>;
    sdmmc {
        compatible = "zephyr,sdmmc-disk";
        status = "okay";
    };
};

&edma0 {
    status = "okay";
};

/* GPT and Systick are enabled. If power management is enabled, the GPT
 * timer will be used instead of systick, as allows the core clock to
 * be gated.
 */
&gpt_hw_timer {
    status = "okay";
};

&systick {
    status = "okay";
};

&wdog1 {
    status = "okay";
};

&enet {
    status = "okay";
    int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>;
    reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>;
    ptp {
        status = "okay";
    };
};

&sai1 {
    status = "okay";
};

zephyr_udc0: &usb1 {
    status = "okay";
};

&mailbox_a {
    status = "okay";
};

3. Changed the Cmake file

 zephyr_library()
    set(RT1170_BOARD_DIR
    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}")
  if(CONFIG_BOOT_FLEXSPI_NOR)
    # Include flash configuration block for RT1170 EVK from NXP's HAL.
    # This configuration block may need modification if another flash chip is
    # used on your custom board. See NXP AN12238 for more information.
    zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)

    zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
    zephyr_compile_definitions(SKIP_DCDC_ADJUSTMENT)
    zephyr_library_sources(${CMAKE_CURRENT_SOURCE_DIR}/xip/flexspi_nor_config.c)
    zephyr_library_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/board)
    zephyr_library_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/xip)
    zephyr_library_sources(${CMAKE_CURRENT_SOURCE_DIR}/board/board.c) #not sure about this?
    zephyr_library_sources(${CMAKE_CURRENT_SOURCE_DIR}/board/clock_config.c) #not sure about this
  endif()
if(CONFIG_DEVICE_CONFIGURATION_DATA)
    # Include device configuration data block for RT1170 EVK from NXP's HAL.
    # This configuration block may need modification if another SDRAM chip
    # is used on your custom board.
    zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1)
    zephyr_library_sources(${CMAKE_CURRENT_SOURCE_DIR}/xip/dcd.c)
else()
    if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000)
      message(WARNING "You are using SDRAM as RAM but no device "
        "configuration data (DCD) is included. This configuration may not boot")
    endif()
  endif()
endif()

if(CONFIG_MCUX_GPT_TIMER)
  message(WARNING "You appear to be using the GPT hardware timer. "
    "This timer will enable lower power modes, but at the cost of reduced "
    "hardware timer resolution")
endif()

# Include directories if needed
message("tq_mba117x included") 

4. Changed Kconfig:defconfig

# Copyright 2021,2023 NXP
#
# SPDX-License-Identifier: Apache-2.0
#

CONFIG_BOARD_TQMBa117x_CM7=y
CONFIG_BOOT_FLEXSPI_NOR=n
CONFIG_SOC_MIMXRT1176_CM7=y
CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_DEBUG=y
CONFIG_DEBUG_INFO=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
CONFIG_FPU=y

#NOR_FLASH-IMAGE
CONFIG_CODE_FLEXSPI=y
CONFIG_FLASH=y
CONFIG_XIP=y
CONFIG_FLASH_BASE_ADDRESS=0x30000000
CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400
CONFIG_FLASH_SIZE=64000

CONFIG_CODE_ITCM=y

5. Changed Kconfig

# MIMXRT1170-EVK board

# Copyright 2021,2023 NXP
# SPDX-License-Identifier: Apache-2.0

if BOARD_TQMBa117x_CM7

config BOARD
    default "tqmba117x_cm7" if BOARD_TQMBa117x_CM7

choice CODE_LOCATION
    default CODE_FLEXSPI if CPU_CORTEX_M7
    default CODE_OCRAM if CPU_CORTEX_M4 && SECOND_CORE_MCUX
    default CODE_SRAM0 if CPU_CORTEX_M4
endchoice

# Only use DCD when booting primary core (M7)
config DEVICE_CONFIGURATION_DATA
    default n if CPU_CORTEX_M7

#config CONFIG_NXP_IMX_RT_BOOT_HEADER
#   default n if CPU_CORTEX_M7

config NXP_IMX_EXTERNAL_SDRAM
    default n if CPU_CORTEX_M7

config BUILD_OUTPUT_INFO_HEADER
    default y

if DISK_DRIVERS

config IMX_USDHC_DAT3_PWR_TOGGLE
    default n

endif # DISK_DRIVERS

if FLASH

choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
    default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
    default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
endchoice

endif #FLASH

if NETWORKING

config NET_L2_ETHERNET
    default n if CPU_CORTEX_M7 # No cache memory support is required for driver

config ETH_MCUX_PHY_RESET
    default n

endif # NETWORKING

endif

6. Added xip

I added our own flexspi_nor_config files which are proved to be working (it worked on bare metal).

While Debugging it looked like this:Debugging

7. I also tried:

This

with Configs Build

still not working.

Question: Does someone have an idea what I'm doing wrong? I'm desperately searching for help! Thx for every clue!

0

There are 0 answers