Why TX descriptor ring size should be 4 times that of RX descriptor ring size?

Question

I was reading Performance Optimization Guidelines for DPDK based applications and it is recommended that TX ring size should be 4 times that of RX ring size. I think Intel guys got this number empirically. Is there any reason to allocate the ring size in 1:4 ratio.

Here is the link for the performance guidelines:

Answer 1

From https://communities.intel.com/community/tech/wired/blog/2011/06/24/parameter-talk-tx-and-rx-descriptors

You can see the “Transmit buffers” are below it. To modify the number of descriptors you just increase the value. In our Windows offerings there will be a limit of 2048 and it must be in increments of 8. On the Transmit side the starting value is 512, but the same rules of 2048 by 8 still apply. Why more TX than RX? Our architecture favors the nondeterministic RX side for priority so there is more turnover of descriptors than the TX side. Plus the O/S can sometimes not return TX assets back to the driver in a timely fashion.