Why mixed signal output only changes at 1ns,2ns,3ns ...?

Question

I'm trying to simulate analog & digital simulation (Cadence Virtuoso version 6)

I make simple counter in verilog code and I succeed to check digital simulation. But when I tried mixed signal simulation (using only 2 inverter chain for analog part for Clk // reset to digital counter), I found that the digital output only changed with multiple time of 1ns (1ns, 2ns, 3ns, 4ns)

Even I make Clk period 100ps, counter changes only 1ns, 2ns, 3ns. (In verilog simulation, it was perfectly OKAY.)

Answer 1

Check your timescale. I expect you will have something like: `timescale 1ns / 1ns The first value is the unit, the second the resolution. As the initialization is different for digital and mixed signal simulators this might be different in both cases. Otherwise it might be due to the connect modules you probably have inserted between analog and digital domains (only in the ams case).