The Apple A7 microarchitecture has 2 branch units and an indirect branch unit. Since the A7 is a modern superscalar out of order cpu with a reasonably deep pipeline (read that as a significant penalty for speculation failure), it makes sense that it has branch prediction for conditional branches. Moreover, it makes sense that since indirect branches are a completely different animal than conditional branches that there would be a separate indirect branch processor.
But why the 2 branch units? It makes sense that there would be 2 types types of branch units. But then it doesn't make sense (to me at least) that the A7 could process 2 branches at the same time. Does not compute. So is there a further specialization of conditional branches?
Does Apple provide any guidance like ARM's Software Optimization Guide for its ARMv8 CPUs which would answer this question? Nope, the LLVM td files isn't a substitute for that sort of Guide.