When the name of bus is only used instead of [a:b], does vivado consider its all bits or just least significant bit

Question

module sillyfunction(input logic [3:0] d0,d1, input logic s, output logic [3:0] y, z);
   assign y = d0; // does this considers 1 bit or all bits of busses?

   anothersillyfunction instance(d1,z) // when this function is fed with these inputs, does it consider 1 bit of busses or all bits of busses?

endmodule

My question is when we want to perform function on specified bits we write something like "assign y[1:0] = d0[1:0];". However, if we don't specify bits what does vivado consider? In other words writing "y or y[3:0]" are the same? Are writing " assign y[3:0] = d0[3:0];" and " assign y = d0;" the same? How system considers a buss when it is just used with its name?

Answer 1

You should not use part select if your intent is selecting the entire range. In fact, y is not the same as y[3:0] when it comes to signed arithmetic. A select of a variable is always unsigned. If you declared it as

logic signed [3:0] y;
...
if (y[3:0] < 0) .. this could never be true