Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!
What' s the difference between <= and := in VHDL
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The rules are a little more complex than this, but basically: you use
<=
to do signal assignment, which takes effect on the next delta cycle. You use:=
to do variable assignment, which takes place immediately. So if you have a signal, you always use<=
. If you have a variable, you always use:=
.Some places where this is not quite that case that you will commonly run into, for instance, initialization, where
:=
is used even for signals.So: