I have the following specifications of an ARM based SoC:
- L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU
- L2 Cache = 1 MB, 64 B/line, 16-WAY
- L1 Data TLB (for loads): 32 entries, fully associative
- L2 Data TLB: 512 entries, 4-WAY
- PDE Cache: 16 entries (one entry per 1 MB of virtual space)
And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure.
Answer
It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented separately from TLB.
The Cortex-A15 MPCore processor implements dedicated caches that store intermediate levels of translation table entries as part of a table walk.
That's interesting. ARM does not name the existence of this PDE cache in Cortex-A15, Cortex-A57 documentations and ARMv7 and ARMv8 programming guides.
PDE generally stands for Page Directory Entry so this may be a dedicated cache to store these entries and write the TTBR register when doing an address translation.
ARM has some "intermediate table walk caches" that are associated with an ASID field (address space identifier) and VMID field (virtual machine identifier) so it seems like PDE cache and intermediate table walk cache are related. In the documentation, "intermediate table walk caches" store intermediate levels of translation table entries ... so this may well be the page directory entries.