VHDL using two components from a second file

Question

I have a problem with my VHDL code, I use mypackage.VHD which contains all my components. So here I have added USE WORK.mypackage.ALL; to use the necessary components for this part. This part uses 2 components, one of them gives me an error when I try to compile the file. If I include the 2 components exactly in the same format, I copy pasted the components from mypackage.VHD to this one and It worked, but once I delete them to use them from mypackage.VHD it gives me error. I cant figure out what is the problem thank you very much in advanced for helping.

In short: I have 2 VHD file, mypackage.VHD,with my all my components and the second one (alu.VHD) that uses mypackage.VHD components with (USE WORK.mypackage.ALL;), looks like it cant identify the alu_1 components from mypackage.VHD. But dont know why.

Here is the error:

** Error (suppressible): C:/../alu_32.vhd(47): (vcom-1141) Identifier "alu_1" does not identify a component     declaration.

The 2 components that my code uses: alu_32 has no error, but alu_1 has an error when it tries to use it from mypackage.VHD.

COMPONENT alu_1
    PORT (
        a, b, c_in, less : IN STD_LOGIC;
        ALUControl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        c_out, result, set : OUT STD_LOGIC
        );
END COMPONENT;

COMPONENT alu_32
    GENERIC (ALU_SIZE : INTEGER := 31); -- Il suffit de chager la valeur 31 a celle de la taille de lALU desiree!
    PORT (
        SrcA, SrcB : IN std_logic_vector(ALU_SIZE DOWNTO 0);
        ALUControl : IN std_logic_vector (3 DOWNTO 0);
        c_out : OUT std_logic;
        Result : OUT std_logic_vector (ALU_SIZE DOWNTO 0);
        zero : OUT std_logic
        );
END COMPONENT;

My code:

LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.std_logic_arith.ALL;
  USE ieee.std_logic_unsigned.ALL;
  USE WORK.mypackage.ALL;


  ENTITY alu_32_generic IS
GENERIC (ALU_SIZE : INTEGER := 31); -- Il suffit de chager la valeur 31 a celle de la taille de lALU desiree!
PORT (
    SrcA, SrcB : IN STD_LOGIC_VECTOR (ALU_SIZE DOWNTO 0);
    ALUControl : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
    c_out : OUT STD_LOGIC;
    result : OUT STD_LOGIC_VECTOR (ALU_SIZE DOWNTO 0);
    zero : OUT std_logic
    );
  END alu_32_generic;
  ARCHITECTURE alu_32 OF alu_32 IS

SIGNAL less_i : std_logic_vector (ALU_SIZE DOWNTO 0);
SIGNAL result_i : std_logic_vector (ALU_SIZE DOWNTO 0);
SIGNAL c_in_i : std_logic_vector (ALU_SIZE + 1 DOWNTO 0);
SIGNAL set : std_logic_vector (ALU_SIZE DOWNTO 0);


     BEGIN
zero <= result_i(31) OR result_i(30);

GEN_REG : FOR i IN ALU_SIZE DOWNTO 0 GENERATE
    alu_32 : alu_1
    PORT MAP(
        a => SrcA(i), 
        b => SrcB(i), 
        c_in => C_in_i(i), 
        ALUControl => ALUControl, 
        c_out => C_in_i(i + 1), 
        less => less_i(i), 
        set => set(i), 
        result => result_i(i)
    );

END GENERATE GEN_REG;   

c_in_i(0) <= ALUControl(2);
c_out <= C_in_i(ALU_SIZE + 1);
less_i(0) <= set(31);
less_i(ALU_SIZE DOWNTO 1) <= (OTHERS => '0'); 
result(ALU_SIZE DOWNTO 0) <= result_i; 
   END alu_32;

Answer 1

Without identifying which is line 47 (your example line counts don't match) you could note that for the entity alu_32_generic declaration:

  ENTITY alu_32_generic IS

The architecture entity name:

  ARCHITECTURE alu_32 OF alu_32 IS

doesn't match.

After correcting the entity name in the architecture declaration and commenting out the three use clauses not needed:

  -- USE ieee.std_logic_arith.ALL;
  -- USE ieee.std_logic_unsigned.ALL;
  -- USE WORK.mypackage.ALL;

Your code then analyzes (which is what vcom does).

Note that if you enable the use clause more mypackage a declaration found as an architecture declarative item will supplant the one in the package. The use clause is not affecting your problem.

From verror:

vcom Message # 1141:
The syntax requires a component name. The name given does not denote a component declaration.

You could note the two usages of alu_1 in your code appear valid. The closest to line 47 of your example appears on line 40 (second line below):

GEN_REG : FOR i IN ALU_SIZE DOWNTO 0 GENERATE
    alu_32 : alu_1

You could also note the first occurrence is in the component declaration immediately within the architecture declaration:

  ARCHITECTURE alu_32 OF alu_32 IS


COMPONENT alu_1
    PORT (

Which raises the question as to whether or not you also have an entity declaration for alu_32 lurking around.

The moral of the story here is don't re-declare things you don't need to and get the entity name right in an architecture declaration.