VHDL : Internal signals are undefined even when defined in the architecture declaration section

Question

So I've been working on some homework for my VHDL course and I can't seem to understand this problem. The point here is to create the adder/subtractor of an ALU that works both on 2's complement and unsigned 32-bit buses, which is why I have a condition called sub_mode ( A - B = A + !B + 1 ) which will also be the carry-in when activated. The rest of the different inputs and outputs are pretty self-explanatory. My problem is with the testbenching of such component where, even though carry_temp and r_temp have been initialized in declaration section of the architecture, end up showing up undefined. I have guessed that it is due to the for loop within the process screwing everything up. Would that be an accurate guess? And if yes, is it possible to proceed to add two bit buses together without having to fully create an n-bit adder made from n 1-bit adder components?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_sub is
port(
    a        : in  std_logic_vector(31 downto 0);
    b        : in  std_logic_vector(31 downto 0);
    sub_mode : in  std_logic;
    carry    : out std_logic;
    zero     : out std_logic;
    r        : out std_logic_vector(31 downto 0)
);
end add_sub;

architecture synth of add_sub is

signal cond_inv : std_logic_vector(31 downto 0);
signal carry_temp : std_logic_vector(32 downto 0) := (others => '0');
signal r_temp : std_logic_vector(31 downto 0) := (others => '0');

begin           
behave : process(a,b,sub_mode)
begin 
    if sub_mode = '1' then 
        cond_inv <= b xor x"ffffffff";
    else
        cond_inv <= b;
    end if; 
    carry_temp(0) <= sub_mode;
    for i in 0 to 31 loop
        r_temp(i) <= a(i) xor cond_inv(i) xor carry_temp(i);
        
        carry_temp(i+1) <= 
            (a(i) and cond_inv(i)) or
            (a(i) and carry_temp(i)) or
            (cond_inv(i)and carry_temp(i));
    end loop;
    if r_temp = x"00000000" then 
        zero <= '1';
    else 
        zero <= '0';
    end if;
    r <= r_temp;
    carry <= carry_temp(32);
end process behave;
end synth;