VHDL Booth algorithm

Question

I am trying to implement Booth algorithm in VHDL. I have implemented the ALU, the clock and the shift register so far. Now I want to use these modules to implement the last module which is the actual algorithm, but I do not know how to use these module in other modules.

Here is my alu module:

library ieee;
use ieee.numeric_bit.all;


entity alu is
 port ( bus_a : in bit_vector(7 downto 0);
 bus_b : in bit_vector(7 downto 0);
 state : in bit_vector (2 downto 0);
 out_c : out bit_vector(7 downto 0));
end alu;


architecture behave of alu is

begin

process(bus_a, bus_b, state)

begin
case state is
    when "000" => 
    out_c<= bit_vector(unsigned(bus_a) + unsigned(bus_b)); --addition 
    when "001" => 
    out_c<= bit_vector(unsigned(bus_a) - unsigned(bus_b)); --subtraction 
    when "010" => 
    out_c<= bit_vector(unsigned(bus_a) - 1); --sub 1 
    when "011" => 
    out_c<= bit_vector(unsigned(bus_a)+ 1); --add 1 
    when "100" => 
    out_c<= bus_a and bus_b; --AND gate 
    when "101" => 
    out_c<= bus_a or bus_b; --OR gate 
    when "110" => 
    out_c<= not bus_a ; --NOT gate 
    when "111" => 
    out_c<= bus_a xor bus_b; --XOR gate 
    when others =>
    NULL;
end case; 

end process; 

end architecture behave;

I have my shift register:

entity shift_reg is
    generic(n:integer:=8; delay:time :=10ns);
    port(parallel_in: in bit_vector(n-1 downto 0);
        parallel_out: out bit_vector(n-1 downto 0);
        clock, reset, load, shift, serial_in: in bit;
        serial_out: out bit);
end shift_reg;

architecture behave of shift_reg is

begin

process(clock, reset)
    variable temp: bit_vector(n-1 downto 0);

begin
    if reset='0' then 
        temp:=(others=>'0');
    elsif clock='1' and clock'event and clock'last_value='0' then
        if shift='1' then
            serial_out <= temp(0) after delay;
            temp:= temp sll 1;
            temp(n-1):= serial_in;
        elsif load='1' then 
            temp:=parallel_in;
        end if;
    end if;
    parallel_out <= temp after delay;

end process;
end architecture behave;

and the clock generator:

ENTITY clk_gen IS
    GENERIC(t_high: TIME:=30ns; t_period: TIME:=50ns; t_reset: TIME:=10ns);
    PORT(clock: OUT BIT:='1'; reset : OUT BIT);
END clk_gen;
ARCHITECTURE behave OF clk_gen IS
BEGIN
    reset<='0', '1' AFTER t_reset;

    PROCESS
    BEGIN
        clock<='1', '0' AFTER t_high;
        WAIT FOR t_period;
    END PROCESS;
END ARCHITECTURE;

Because I am new to VHDL I do not not how I can use these functions(syntax and so on), which I need in my final algorithm. Any help on how to integrate these modules in the third module,which would be the booth algorithm, would be much appreciated. Thanks in advance!

EDIT: Here I have a part of the Booth algorithm implementation with component instantiations:

   entity booth_mul is
    generic(x : integer := 8);
    port(
        bus_x : in bit_vector((x - 1) downto 0);
        bus_y : in bit_vector((x - 1) downto 0);
        out_z : out bit_vector((2*x - 1) downto 0));
end booth_mul;

architecture behave of booth_mul is

component alu is
        port(bus_a : in bit_vector(7 downto 0);
        bus_b : in bit_vector(7 downto 0);
        state : in bit_vector (2 downto 0);
        out_c : out bit_vector(7 downto 0));
    end component;

component shift_reg is
        generic(n: integer:=8; delay: time:=10ns);
        port(parallel_in: in bit_vector(n-1 downto 0);
        parallel_out: out bit_vector(n-1 downto 0);
        clock, reset, load, shift, serial_in: in bit;
        serial_out: out bit);
    end component;

begin

process(bus_x, bus_y, out_z)
variable st: bit_vector

begin

for i in 0 to x loop

case st is
    when "00" 
--I want here to do an arithmetic shift, behaviour that is implemented in my shift_reg, can I call it somehow or how should I use it ?



end process;
end architecture behave;

I added above in my comments what I want to implement and is unclear for me.