Vector of registers size can not be parametrized by module parameter

Question

I want to use module parameter as a size parameter of Vector, which contains registers, and I try next code:

package Test;
import Vector      :: *;
(* synthesize *)
module mkTest #(
  parameter UInt#(32) qsize
) (Empty);
  Vector#(qsize,Reg#(Bit#(8))) queue <- replicateM (mkReg (0));
endmodule
endpackage

But compiling this module with bsc I get next error message:

Verilog generation
bsc -verilog -remove-dollar Test.bsv
Error: "Test.bsv", line 9, column 11: (T0008)
  Unbound type variable `qsize'

bsc version:

Bluespec Compiler (build e55aa23)

If I use not Registers as a type of Vector elements, everything is OK. Next code will produce no errors:

package Test;
import Vector      :: *;
(* synthesize *)
module mkTest #(
  parameter UInt#(32) qsize
) (Empty);
  Vector#(qsize,Bit#(8)) queue = replicate(0);
endmodule
endpackage

And I can not understand, why qsize is Unbound as it is clearly declared as a parameter? If I did something wrong, could you please help me and explain, how to make parameterized size Vector of Regs correctly?

Answer 1

I have asked this question in one of the Bluespec repositories on github and Rishiyur S. Nikhil gave me a very full explanation. See https://github.com/BSVLang/Main/issues/4

In short: Vector as a first parameter needs a type, not UInt (or Int or something else). So the right way to do will be:

1. Make an interface for module and make it type-polymorphic
2. Use type from that interface as a Vector size parameter

package Test;
import Vector      :: *;

interface Queue_IFC #(numeric type qsize_t);
  method Bool done;
endinterface

module mkQueue ( Queue_IFC #(qsize_t) );
  Vector #(qsize_t, Reg #(Bit #(8))) queue <- replicateM (mkReg (0));
endmodule

endpackage