Variable assignment in Makefile Prerequisites

Question

I'm looking through the Linux kernel code to try and understand how the image is built. In the scripts/makefile.build Makefile, there are some lines that look like this:

$(real-objs-m)    :   part-of-module :=y
$(real-objs-m)    :   quiet_modtag := [M]
$(multi-objs-m)   : modname=$(modname-multi)

They don't look like target-and-prerequisites lines nor static pattern rules. I've been already googled a lot, but nothing seems an answer. What do these syntaxes mean?

Answer 1

This is target-specific variable values.

From the documentation https://www.gnu.org/software/make/manual/html_node/Target_002dspecific.html

This feature allows you to define different values for the same variable, based on the target that make is currently building. As with automatic variables, these values are only available within the context of a target’s recipe (and in other target-specific assignments).

There is one more special feature of target-specific variables: when you define a target-specific variable that variable value is also in effect for all prerequisites of this target, and all their prerequisites, etc. (unless those prerequisites override that variable with their own target-specific variable value).