Trouble trying to disable L2 cache on BeagleBone Black

Question

First of all, I'm a total beginner on ARM programming. I want to make some analysis with my L2 cache disabled. I'm running a U-boot environment, bare-metal, on my BeagleBone Black and I'm trying to disable the cache following the steps provided on this link:

1. Disable the C bit.
2. Clean and invalidate the L1 and L2 caches.
3. Disable the L2 cache by clearing the L2EN bit to 0.
4. Enable the C bit.

My code is something like this:

asm volatile("MRC p15, 0, %0, c1, c0, 0\t\n": "=r"(controlRegister)); //Retrieve Control Register
controlRegister = controlRegister & ~(1u << 2); //change Bit C to 0;
asm volatile ("MCR p15, 0, %0, c1, c0, 0\t\n" :: "r"(controlRegister)); //write new value

I know this is only the first step (disable C bit), but I'm having trouble accomplishing it. The problem is, when I try to write the new value and then check if it was written correctly, the value retrieved is 00000000.

In ARM's forum I was told that I need to be on supervisor mode, but on the documentation it says, and I quote, “Supervisor mode is a protected mode for the OS” and since I don’t have an OS (I’m running bare-metal), I don't know if there is this “mode abstraction”.

Do you have any ideas?