I have an SVA question :
Let's say we have signal wpo, and 19-21 clocks cycles later, we have wpo(the value at time 0) == out. How to write an SVA for that. I tried this but it doesn't work
logic [103:0] temp;
property check_property;
@(posedge clk) disable iff (rst)
##[19:21] (temp === wpo);
endproperty
check_property_A: assert property (check_property);
always_ff @(posedge clk) begin
temp <= out;
end
So to recap wpo should have the value that out had 19-21 cycles earlier.
You need to declare
temp
as a local variable of the property.