state transitions dependent upon input event VHDL

Question

I am a newbie in VHDL. I am currently working on an FSM and I want my state machine to change states only when my input changes. What changes should I make in the following code?

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           x_in : in STD_LOGIC;                         -- input Bitstream  
           y_out : out STD_LOGIC_VECTOR (1 downto 0));  -- Encoded output
end fsm;

-----------------------------------------------------
architecture Behavioral of fsm is

  -- Building an Enumerated type for the state machine
  type state_type is (s_idle,s1,s2,s3,s4);  -- constraint length = 3, Hence number of Regs = 2 therefore Number of states = 4
  signal state, next_state: state_type ;    -- Registers to hold the Present and next states

begin
-----------------------------------------------------
  process1: process (reset, clk)             --  Sequential Logic Selection process:
     begin

          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 1

Assuming that you want to make the FSM change state when -->

1. The clk is high
2. The value of X_in changes

Also, I'll assume that your next_state variable is some combinational function of state which you haven't mentioned. Just one change will suffice, add X_in to your process sensitivity list.

-----------------------------------------------------
  process1: process (X_in, reset, clk)             --  Sequential Logic Selection process:
     begin

          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 2

Assuming that the x_in input is synchronized to clk, this will do what you describe:

 process1: process (reset, clk)
 begin

      if (reset ='1') then  
          state <=s_idle;         
      elsif (clk='1' and clk'Event) then
          x_in_prev <= x_in;
          if x_in_prev /= x_in then
              state <= next_state;
          end if;
      end if;
 end process process1;

You need to define the x_in_prev signal in your architecture for this to compile.