Need help in designing a six-stage pipelining with superscalar processor with two execution units. Six stages are Instruction Fetch (IF), Instruction Decode (ID), Read from Registers (RR), 2-cycle Execution (EX), Write back result (WB). Instructions cannot be reordered. In an execution cycle, at most one instruction issued could be memory (load or store) related and at most one instruction could be non-memory dealing with arithmetic operations with registers. Latency is 3 cycles for Load operations and 2 cycles for others. Latency is considered as the time-delay cycles between issue cycles for dependent instructions. Now, we have the following instruction sequence:
(1) LD R21, (R20)
(2) LD R18, (R17)
(3) ADD R16, R21, R18
(4) LD R15, (R14)
(5) ADD R13, R12, R11
(6) SUB R23, R22, R24
(7) ST (R23), R10
(8) ADD R4, R21, R18
(9) ST (R3), R2
(10) ST (R1), R4
How long does the program take to issue, considering that an instruction is said to have issued when it passes from the RR stage to the EX stage.
My workout is as follows:
RAW conflicts exist in (1) and (3), (2) and (3), (2) and (8), (2) and (8), (6) and (7). Thus, the timing diagram is :
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
I01: IF ID RR EX EX WB
I02: -- IF ID RR EX EX WB
I03: -- -- -- -- IF ID RR EX EX WB
I04: -- -- -- -- IF ID RR EX EX WB
I05: -- -- -- -- -- IF ID RR EX EX WB
I06: -- -- -- -- -- -- IF ID RR EX EX WB
I07: -- -- -- -- -- -- -- -- IF ID RR EX EX WB
I08: -- -- -- -- -- -- -- -- IF ID RR EX EX WB
I09: -- -- -- -- -- -- -- -- -- IF ID RR EX EX WB
I10: -- -- -- -- -- -- -- -- -- -- IF ID RR EX EX WB
Please comment on the solution approach.