i am trying to do a fulladder of 4 bits from a fulladder 1bit but the plataform vivado that i am using give a syntaxis error but i don t know why? here is the first module (the name is HA2(Fulladder1bits(i have to change the letters HA2 for FA but i know how to do it yet)))

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HA2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s : out  STD_LOGIC;
           cin : in  STD_LOGIC;
           count : out  STD_LOGIC);
end HA2;

architecture Behavioral of HA2 is

begin

s <= a xor b xor cin;
count <= (a and b) or (cin and (a or b));

end Behavioral;

and the error is in this next module (named "fulladder4bits" ) :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder4bits is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           S : out STD_LOGIC_VECTOR (3 downto 0);
           C3 : out STD_LOGIC);
end fulladder4bits;

architecture Behavioral of fulladder4bits is

COMPONENT HA2
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s : out  STD_LOGIC;
           cin : in  STD_LOGIC;
           count : out  STD_LOGIC);
end COMPONENT;
signal C0,C1,C2 : std_logic ;
begin

fa1 : HA2 port map(A(0),B(0),'0',S(0),C0) ;**HERE the plataform vivado give me a syntaxis error but i don t know why 
fa2 : HA2 port map(A(1),B(1),'C0',S(1),C1) ;**HERE 
fa3 : HA2 port map(A(2),B(2),'C1',S(2),C2) ;**HERE 
fa4 : HA2 port map(A(3),B(3),'C2',S(3),C3) ;**HERE 

end Behavioral;

however with the errors and everything i could do the synthesis and the implementation so i really don t know what is the problem.

2 Answers

1
Alimpk On Best Solutions

The order of the ports in the component is important. Instantiate has used with another order. The order of s and cin is not correct. Therefore, you can use to way to solve problem.

fa1: HA2 port map(A(0), B(0), S(0),'0', C0);
fa2: HA2 port map(A(1), B(1), S(1), C0, C1);
fa3: HA2 port map(A(2), B(2), S(2), C1, C2);
fa4: HA2 port map(A(3), B(3), S(3), C2, C3);

or (this way is better choice)

fa0:HA2 port map(a=>A(0), b=>B(0), cin=>'0', s=>S(0), count=>C0);
fa1:HA2 port map(a=>A(1), b=>B(1), cin=>C0, s=>S(1), count=>C1);
fa2:HA2 port map(a=>A(2), b=>B(2), cin=>C1, s=>S(2), count=>C2);
fa3:HA2 port map(a=>A(3), b=>B(3), cin=>C2, s=>S(3), count=>C3);

The second problem of your code is 'C0' ('C1', 'C2') in port map. it should be C0 (C1, C2).

0
mrpepo877 On

this solve my problem but i really don t know why :

fa0:HA2 port map(a=>A(0),b=>B(0),cin=>'0',s=>S(0),count=>C0);
fa1:HA2 port map(a=>A(1),b=>B(1),cin=>C0,s=>S(1),count=>C1);
fa2:HA2 port map(a=>A(2),b=>B(2),cin=>C1,s=>S(2),count=>C2);
fa3:HA2 port map(a=>A(3),b=>B(3),cin=>C2,s=>S(3),count=>C3);