I am designing an application based on a ADSP-SC589 from Analog Devices which includes two SHARC+ cores and a ARM Cortex A5.
A shared memory space located on L2 is available to any cores. I am trying to figure out how, the different cores can prevent data corruption during the read/write of multibytes data.
For example, if I want to write a 64-bit value (two distinct writes). I must tell the other cores to not read that value until it's ready. In other words I must lock this region of memory for a short period of time.
Since each core run at different speed on their own loop, I can't imagine any interrupts based solution. I also did not find any magic peripheral on the processor that allow to lock/unlock a certain region of memory causing stalls on other cores pipelines (I may not used the proper keywords to find this magic feature).
The naive solution I imagined was this:
#define CORE0 (1<<3) // Highest priority
#define CORE1 (1<<2)
while((interlock.request |= CORE0) > CORE0);
foo = sharedmemory.foo;
bar = sharedmemory.bar;
interlock.request &= ~CORE0;
Unfortunately the interlock.request |= CORE0 involves both a ready and a write access so this solution does not work without true or/and operations on the shared memory. Implementing the Dekker's algorithm seems to be the best solution, but it looks resources consuming.
What is the typical approach to use for this kind of issues?
I am sure a 3-cores processor must have an hardware based sort of mutex. Isn't?