I am using Vivado for running my Verilog codes. Even though I do not see any errors while running synthesis and implementation, bitstream cannot be built.
This is the error I get:
ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.
Which also suggests:
To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.
Which comes down to how can I script in Tcl
using Vivado? I added the suggested command to the tcl console but I still get the same error.
I sugest you do what the tool is telling to do, which is specify IO standard for your top level ports, for example, if you have
sys_rst_n
top level port you may add the following line to your.xdc
constraint file:of course you should change
LVCMOS18
to match IO standard of you port.The error you get is really not a
Tcl
issue.