I have a module hierarchy and I want to generate verilog with a postfix to the module names. is there a way to do this at compile time ?
Example:
(*synthesize*)
module mk_abc(Empty);
Say I compile this 3 times, I want the generated verilog to be mk_abc_1, mk_abc_2, mk_abc_3. Can I somehow specify what the post-fix should be ? Is there a way to do this at compile time ? Or what is the best way to get this done?
Note: these modules (and their sub-modules) use ifdefs. The values for these compile-time macros (ifdefs) can change every time I compile. that is, mk_abc_1, mk_abc_2, and mk_abc_3 can use three completely different set of values for the macros, but the names of the macros remain the same (they're the same module).
Thanks in advance.
I'm opening a question here, hoping to get a faster answer. I have also asked the same question here. I have no idea how to get started with this.