Hi I'm trying to use Qsys to create a PLL. The PLL is intended to be used with a serial interface on am FPGA. When I start Modsim to simulate. I get no output from the PLL. Investigating a bit further I tried to load just the PLL in modsim and I get the following error.
** Error: (vsim-3039) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/PLL1.vhd(49): Instantiation of 'PLL1_altpll_0' failed.
Region: /pll1 Error loading design
Of the 4 modules seen in the PLL1 entity see below:
Modsim will only except the bottom two. The "pll1_altpll_0" and "pll1_altpll_0_altpll_4242" modules display
Loading PLL1.PLL1_altpll_0_dffpipe_l2c Loading PLL1.PLL1_altpll_0_altpll_4242 ** Error: (vsim-3033) C:/altera/13.0sp1/____PROJECT____/TSSD/PLL/PLL1/synthesis/submodules/PLL1_altpll_0.v(192): Instantiation of 'cycloneiii_pll' failed. The design unit was not found.
When opened within modsim.
Has anyone had a similar problem or know where I am going wrong using either Modsim or Qsys?
Many Thanks D