I've a basic question regarding of Front Side Bus (FSB) characteristics
Consider for instance Pentium 4 FSB: it is a "quad-pumped" bus in which FSB'clock (BCLK) is 100Mhz but data transfert is at 400 MT/s (4 Transfers/Cycle).
AFAIK to complete a transfer to/from memory are needed five phases: Request Phase, Snoop Phase, Response Phase and Data Phase. Some of them (e.g. Request phase) requires one bus clock cycle (BCLK).
So, even if the process of sending data is quad-pumped, the net FSB transfert rate cannot be BCLK x 4 because of the (necessary) previous associated phases (namely Request, Snoop and Response)
Does it make sense ?
At a deeper look to me it seems the "pipelined" FSB architecture is the answer to the original question. Having separate lanes for address, data (64 bit data bus widht) and control, Pentium 4 FSB runs in a pipelined mode maximizing DRAM module throughput
Someone can confirm my understanding ? Thanks.