Preprocessor directives in linux makefile

Question

How do you use commands like #define and !include in linux makefile for the g++ compiler? My understanding is that # creates a comment line so wont #define just be a comment? Thanks for the help

Answer 1

I typically define a variable at the top of the file, and set it equal to the #define values I want like this:

DEFINES=-DSOMETHING -DSOMETHING_ELSE

For includes, g++ accepts search paths from the command line with -I. For the makefile you can do the same thing, just make a variable and add the paths:

INCLUDES=-I/path -I/path2

The makefile then just calls the compiler as

g++ $(DEFINES) $(INCLUDES) file.cpp 

Answer 2

Check out this example

# I am a comment, and I want to say that the variable CC will be
# the compiler to use.
CC=g++
# Hey!, I am comment number 2. I want to say that CFLAGS will be the
# options I'll pass to the compiler.
CFLAGS=-c -Wall

all: hello

hello: main.o factorial.o hello.o
    $(CC) main.o factorial.o hello.o -o hello

main.o: main.cpp
    $(CC) $(CFLAGS) main.cpp

factorial.o: factorial.cpp
    $(CC) $(CFLAGS) factorial.cpp

hello.o: hello.cpp
    $(CC) $(CFLAGS) hello.cpp

clean:
    rm *o hello

for more information check these:

http://mrbook.org/blog/tutorials/make/

http://www.cs.umd.edu/class/fall2002/cmsc214/Tutorial/makefile.html