Pipelining -Mips instructions

Question

I have confused by using pipelining in mips instruction. Any help will be great. Thanks in advance.

What is the data dependency in the next two codes? Which of them can be solved by using stall (bubble) or forwarding. You can use the shape 1 for convenience.

          shape 1:

           If-Id-Ex-Mem-Wb

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explanation:

if=instruction fetch

id=instruction decode register fetch

ex=execute

mem=memory access

wb=write back 

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code 1:

add $3,$4,$2

sub $5,$3,$1

lw  $6,200($5)

sw  $6,200($2)

lw  $6,200($3)

add $7,$4,$6

code 2:

add $3,$4,$2

sub $5,$3,$1

lw $6,200($3)

add $7,$3,$6

(sorry for bad post,but i can't yet post an image)

Thanks.

Answer 1

Let's see the first one:

add $3,$4,$2  

sub $5,$3,$1

The result from add is used in sub, therefore there is a data hazard. We have to insert an amount of NOP stages to resolve it. Assuming all instructions take up 5 cycles, we insert 3 NOPs and we're done.

add $3,$4,$2  IF  ID  EX MEM  WB  

sub $5,$3,$1     NOP NOP NOP  IF  ID  EX MEM  WB

We can do this for all subsequent instructions. Now instructions produce new values in the EX and MEM stages. Those values are not written to a register until the WB stage (for learning purposes, let's assume that's true). Since the registers are read in the ID stage, this leaves a window of three cycles for which old incorrect values are "flowing" through the pipeline. Forwarding can help cure this problem in our case above - forward the result from add:EX to sub:ID.

Hope this helps.