Paging and TLB operating systems

Question

I'm really stuck on this question for my OS class, I don't want someone to just give me the answer though, instead if someone could tell me how to work it out.

Example Question:

This system uses simple paging and TLB

• Each memory access requires 80ns

• TLB access requires 10ns

• TLB hit rate is 80%.

Work out the actual speedup because of the TLB?

NOTE: I changed the memory accessed required and the TLB access requires part of the question because as I said I don't want the answer, just a way to work it out.

Answer 1

In case the virtual address translation is cached in the TLB, all we need is one lookup in the TLB that will give us a physical address, and we are done. The interesting part is if we need to do the page table walk. Think carefully about what the system has to do in case it did not find an address in the TLB (well it already had to do a TLB look-up). Memory access takes 80ns, but how many of them do you need to actually get the physical address? Pretty much every paging architecture follows the schema that page-tables are stored in memory and only the entry point, the address that points to the base of the first page table (the root) is in a register.

If you have the amount of time you can calculate the speed-up by comparing it to the TLB access time.

Answer 2

On TLB Hit 80% your required to access time 2ns and to access that page in main memory required 20ns therefore one part is 0.8×(2+20)

On TLB miss i.e. (1-0.8) 20% for that you are checking TLB again so required 2ns when it is TLB miss it will check into Page Table but base Address of Page Table is into Main Memory so it requires 20ns and when it searches into PT it will getting desired Frame and again required memory access time to access data from main memory so miss calculation is 0.2×(2+20+20)

From above 2 :

Effective access time=0.8×(2+20)+0.2×(2+20+20) = 26ns